Self-aligned trench transistor using etched contact
US6924198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2004 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Jan 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A trench-gated MOSFET formed using a super self aligned (SSA) process employs an insulating layer such as a glass layer and a contact mask to define contact openings for electrical connections to source regions of the MOSFET. Use a contact mask and an intervening glass in otherwise self-aligned process reduces the coupling capacitance between source metal and the top of the embedded trench gate. A metal layer deposited to make electrical contact to source regions can be planarized, for example, ground flat using chemical-mechanical polishing to provide a flat surface to avoid formation of conductive traces that extend over the steps that the glass layer forms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.