Thin channel FET with recessed source/drains and extensions

US6924517B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Huajie Chen · Danbury, US
• Bruce B. Doris · Brewster, US
• Philip J. Oldiges · Lagrangeville, US
• Xinlin Wang · Irvine, US
• Huilong Zhu · Poughkeepsie, US

Key dates

• Filing date: Aug 26, 2003
• Grant date: Aug 2, 2005
• Expiry date: Aug 26, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6741

Abstract

A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.