SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING MEMORY CELL SECTION HAVING CAPACITOR OVER BITLINE STRUCTURE AND WITH THE MEMORY AND PERIPHERAL SECTIONS HAVING CONTACT PLUG STRUCTURES CONTAINING A BARRIER FILM AND EFFECTING ELECTRICAL CONTACT WITH MISFETS OF BOTH MEMORY AND PERIPHERAL SECTIONS
US6924525B2 · kind B2 · utility
2Cited by
14References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Aug 19, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
Abstract
The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 Ω/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.