Split gate flash memory cell structure and method of manufacturing the same
US6924527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Mar 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.