Latch circuit with metastability trap and method therefor
US6924682B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for trapping metastability events to provide a metastable-free output signal. Values of an input signal compared to at least three different threshold voltages are latched at a predetermined point in time. A first intermediate signal is activate when all of the at least three corresponding latched values are in a first logic state. A second intermediate signal is activated when all of the at least three corresponding latched values are in second logic state. An output signal is placed in a first predetermined logic state in response to the second intermediate signal and is changed from the first predetermined logic state to a second predetermined logic state in response to the first intermediate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.