SRAM device and a method of powering-down the same
US6925025B2 · kind B2 · utility
59Cited by
1References
20Claims
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Key dates
| Filing date | Nov 5, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Feb 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to the SRAM array having voltage domains defined by a boundary and (3) a power-down voltage controller coupled to the SRAM array and the peripheral circuitry that separately regulates voltages of the SRAM array and the peripheral circuitry to reduce leakage current of the SRAM array and the peripheral circuitry at the boundary during a sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.