Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
US6925550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.