Eric Sprangle
24Patents
8h-index
22Co-inventors
71Inventor score
Filing activity: Jan 2, 2002 → Dec 8, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9170955B2 | Providing extended cache replacement state information | Emerging Cross-Sectional Technologies | 51 | Active |
| US8669990B2 | Sharing resources between a CPU and GPU | Physics | 50 | Active |
| US8683183B2 | Performing a multiply-multiply-accumulate instruction | Physics | 46 | Active |
| US8615647B2 | Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state | Emerging Cross-Sectional Technologies | 25 | Active |
| US8533436B2 | Adaptively handling remote atomic execution based upon contention prediction | Physics | 16 | Active |
| US6925550B2 | Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection | Physics | 14 | Expired |
| US8930722B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 12 | Active |
| US9829965B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 10 | Active |
| US9760162B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 2 | Active |
| US9753530B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 2 | Active |
| US11054890B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 2 | Active |
| US9939882B2 | Systems and methods for migrating processes among asymmetrical processing cores | Emerging Cross-Sectional Technologies | 1 | Active |
| US9910483B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 1 | Active |
| US9110655B2 | Performing a multiply-multiply-accumulate instruction | Physics | 1 | Active |
| US9792115B2 | Super multiply add (super MADD) instructions with three scalar terms | Physics | 1 | Active |
| US9870046B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 1 | Active |
| US9874926B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 1 | Active |
| US11366511B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 0 | Active |
| US10386915B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 0 | Active |
| US10437320B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 0 | Active |
| US8478969B2 | Performing a multiply-multiply-accumulate instruction | Physics | 0 | Active |
| US8933946B2 | Mechanism for effectively handling texture sampling | Physics | 0 | Active |
| US10181171B2 | Sharing resources between a CPU and GPU | Physics | 0 | Active |
| US10409360B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.