System and method for protecting and integrating silicon intellectual property (IP) in an integrated circuit (IC)
US6925614B2 · kind B2 · utility
2Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Jun 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for integrated circuit (IC) design using silicon intellectual property (IP) libraries that permits the protecting of the designs of circuits in the silicon IP while allowing correctness verification of the IC design. A preferred embodiment comprises a phantom cell (for example, phantom cell 505) that contains circuit elements (for example, circuit element EL-A 510) connected to each input/output pin of the phantom cell. The inclusion of the circuit elements permits an engineering design tool to check for improperly connected wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.