Method of manufacturing semiconductor device with interconnections and interconnection contacts and a device formed thereby
US6927126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2004 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Apr 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A second insulating layer is formed on a first insulating layer. A plurality of stacks each including a bit line and a bit line mask are formed on the second insulating layer. A third insulating layer is formed overlying the second insulating layer to fill gaps between the plurality of stacks. A hard mask layer is formed on the third insulating layer. A photoresist pattern is formed on the hard mask layer. The photoresist pattern has an opening region that intersects the plurality of stacks. The hard mask layer and the third insulating layer are sequentially etched, using the photoresist pattern as an etching mask, thereby forming a hard mask pattern and forming a recess in the third insulating layer. The recess exposes a portion of upper sidewalls of the bit line mask. Spacers are formed on the exposed upper sidewalls of the bit line mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.