Forming a retrograde well in a transistor to enhance performance of the transistor
US6927137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Dec 1, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.