Method and structure for BiCMOS isolated NMOS transistor
US6927460B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Feb 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.