Method of manufacturing a semiconductor package for a die larger than a die pad
US6927479B2 · kind B2 · utility
16Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.