Substrate for semiconductor package
US6927485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2002 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Sep 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1536
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate for a semiconductor package is provided, which includes: a core layer; at least a metal layer applied over each of upper and lower surfaces of the core layer, wherein the metal layer on the upper surface forms a plurality of conductive traces each having a terminal, and the metal layer on the lower surface is defined with a conductive region and a surrounding peripheral region, allowing the conductive region to form a plurality of conductive traces each having a terminal; and an insulating layer applied over each of the metal layers, wherein terminals of the conductive traces and at least a corner portion of the peripheral region are exposed to outside of the insulating layers. During fabrication of semiconductor packages, after a post molding curing process, the vertically-stacked substrates can be easily separated by virtue of a gap being formed between exposed corner portions of the stacked substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.