Low skew, power efficient local clock signal generation system
US6927615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A local clock signal generation system is disclosed including multiple local clock buffers each receiving a global clock signal and producing a version of one or more local clock signals derived from the global clock signal. Each local clock buffer includes an input section and an output section. The input sections are substantially identical such that timing differences between the versions of the one or more local clock signals are reduced. An electronic circuit is described including the local clock signal generation system and a latch (e.g., a master latch of a flip-flop). A local clock buffer produces a gating signal and a local clock signal received by the latch. When the gating signal is a certain logic value, the local clock signal is a steady logic value, and the latch produces an input data signal as an output signal. An integrated circuit including the electronic circuit is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.