Bitline equalization system for a DRAM integrated circuit
US6928012B2 · kind B2 · utility
6Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for pre-charging and equalizing potentials on a bitline pair in a DRAM integrated circuit. The system includes an equalization circuit at one position on the bitline pair and another equalization circuit at another position on the bitline pair. As charge is distributed between the bitlines and to/from the pre-charge potential source through multiple conduction paths, the pre-charge and equalization time of the bitlines is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.