Semiconductor memory device
US6928017B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 8, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Sep 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.