Integrated circuit implementing packet transmission
US6928073B2 · kind B2 · utility
4Cited by
60References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The implementation of transactions on an integrated circuit comprising a plurality of functional modules connected to a packet router is described. Each functional module generates request packets for implementing memory access operations, each request packet having an operation field comprising eight bits of which a packet type bit denotes the type of the packet, four operation family bit denote the function to be implemented by the packet and three operation qualifier bits act to qualify the function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.