Memory module and memory component built-in self test
US6928593B1 · kind B1 · utility
28Cited by
18References
64Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2000 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Oct 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory component with built-in self test includes a memory array. An input/output interface is coupled to the memory array and has a loopback. A controller is provided to transmit memory array test data to the memory array to store the memory array test data, and to read the memory array test data from the memory array. A compare register is also provided to compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.