Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits
US6928635B2 · kind B2 · utility
217Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2002 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Sep 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.