Method for programming single-poly EPROM at low operation voltages
US6930002B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2004 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Apr 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a single-poly EPROM cell at relatively low operation voltages (±Vcc) is disclosed. According to this invention, the single-poly EPROM cell includes a P-channel floating-gate transistor formed on an N well of a P type substrate, and an N-channel coupling device. The P-channel floating-gate transistor has a P+ doped drain, P+ doped source, a P channel defined between the P+ doped drain and P+ doped source, a tunnel oxide layer on the P channel, and a floating doped poly gate disposed on the tunnel oxide layer. The N-channel coupling device includes a floating poly electrode, which is electrically connected to the floating doped poly gate of the P-channel floating-gate transistor, and is capacitively coupled to a control region doped in the P type substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.