Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling
US6930004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/299
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.