Feature targeted inspection
US6931297B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2004 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/7065
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.