Apparatus and methods for sharing cache among processors
US6931489B2 · kind B2 · utility
8Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Apr 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface. The system allows an upper-level cache data array to be shared among processors while cache latency is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.