Method and system for translation lookaside buffer coherence in multiprocessor systems
US6931510B1 · kind B1 · utility
7Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2000 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is an apparatus, method, and system for translational lookaside buffer coherency in computer systems having a plurality of processors, each having an associated TLB for storing address translation data, and the computer system having a plurality of independent paths upon which the plurality of processors are distributed and a TLB message transmitted on said plurality of independent paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.