Multiple mode power throttle mechanism
US6931559B2 · kind B2 · utility
31Cited by
39References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | May 14, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline, and to determine a power state for the processor from the monitored activity. One of two or more power control mechanisms is engaged, responsive to the power state of the processor reaching a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.