System and method for designing circuits in a SOI process
US6931607B2 · kind B2 · utility
6Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.