Mask cost driven logic optimization and synthesis
US6931617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2003 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jul 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The cost of making a mask set cost has been dramatically increasing due to demand for very small device sizes as well as higher chip complexity. Thus, users would like to minimize the total mask costs. Current logic synthesis tools can create mask designs based on IC characteristics, e.g. speed, area, and power consumption. Therefore, a method of providing a mask design that can be optimized for cost is described. This method includes accessing cells from a library, wherein each cell includes a mask cost metric. Additionally, the weightings of one or more parameters in a constraints listing can be determined. Of importance, at least one parameter relates to mask cost. At this point, logic synthesis can be performed on the design using both the cells and the constraints listing. Advantageously, the resulting synthesized design can be optimized for mask cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.