Method of making and interconnect structure
US6931726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2003 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of making an interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the method includes the steps of providing a substrate having at least one plated through hole therein, and positioning a first conductive layer and a second conductive layer over the at least one plated through hole on opposing surfaces of the substrate. The method includes positioning a layer of dielectric material thereon on the first conductive layer. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, and at least a pair of conductive layers that can carry signals, and power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.