Recessed tunnel oxide profile for improved reliability in NAND devices
US6933554B1 · kind B1 · utility
4Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2001 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Aug 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved NAND-type memory cell structure having improved reliability and endurance. Since a high risk area for oxide breakdown and/or current leakage exists in the tunnel oxide layer, source/drain overlap region, the present invention provides a NAND-type memory cell fabricated using controlled formation of the tunnel oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.