Method and circuit for optimizing power efficiency in a DC-DC converter
US6933706B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2003 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a turn-on delay control structure (30) includes a sense FET device (31) that is coupled to a switch node (13) in a synchronous DC-DC converter (10). The DC-DC converter includes a high-side switch (11) and a low-side switch (12). The sense FET device (31) senses current conduction in a body diode (18) of the low-side switch (12). A current sensing/comparator circuit (32) coupled to the sense FET (31) detects changes in current conduction. A delay circuit (33) and a clock/logic circuit (32) coupled to the current sensing/comparator circuit (32) predict and adjust delay time in switching between the high-side switch (11) and the low-side switch (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.