Chip card circuit with monitored access to a test mode
US6933742B2 · kind B2 · utility
2Cited by
8References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Aug 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit for monitoring an entry into a test mode of a chip circuit has a fusible link which can be fired via a firing transistor. A flipflop, which permits access to the test mode, is set by a resulting voltage drop, with the aid of an edge detector. The number of times the test mode has been accessed can be detected from the number of fired fusible links.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.