Degenerative inductor-based gain equalization
US6933782B1 · kind B1 · utility
1Cited by
16References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Oct 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.