EEPROM memory protected against the effects from a breakdown of an access transistor
US6934192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.