Semiconductor memory circuit
US6934210B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 9, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.