T1/E1 framer array
US6934304B2 · kind B2 · utility
2Cited by
25References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2001 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Apr 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0608
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system and method for frame detection and generation. Each incoming clock-data stream is divided into two independent data streams: a clock path which preserves the timing of the individual cock domains and a data path which multiplexes an arbitrary number of data streams onto a parallel path. A framer array structure implements a context swap and synchronizes the data streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.