Network interface using programmable delay and frequency doubler
US6934866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.