STI pull-down to control SiGe facet growth
US6936509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Sep 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/891
Abstract
A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.