Method for fabricating a memory device having reverse LDD
US6936515B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Mar 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
Abstract
A method for fabricating a semiconductor device. Specifically, a method that includes forming a source and drain region in a periphery transistor, exhibiting a channel width between the source and drain regions suitable for operation at predetermined voltages. After forming the source and drain regions, to eliminate diffusion of lightly doped drain regions resulting from a later formation of the source and drain regions, forming the lightly doped drain regions adjacent to the source and drain regions of the periphery transistor. After forming the lightly doped drain regions in the periphery transistor, the method includes forming a source region and a drain region in a core memory cell, independent of forming the source and drain regions in the periphery transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.