FASL LLC
30Patents
1Active
30Granted
36Portfolio score
Filing activity: Oct 2, 2000 → Feb 24, 2006 · 1 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6912163B2 | Memory device having high work function gate and method of erasing same | Electricity | 113 | Expired |
| US7122853B1 | Method to improve yield and simplify operation of polymer memory cells | Electricity | 85 | Expired |
| US6949433B1 | Method of formation of semiconductor resistant to hot carrier injection stress | Emerging Cross-Sectional Technologies | 81 | Expired |
| US7033957B1 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Emerging Cross-Sectional Technologies | 42 | Expired |
| US6958511B1 | Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen | Electricity | 42 | Expired |
| US6949481B1 | Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device | Electricity | 33 | Expired |
| US6884681B1 | Method of manufacturing a semiconductor memory with deuterated materials | Electricity | 31 | Expired |
| US6791880B1 | Non-volatile memory read circuit with end of life simulation | Physics | 26 | Expired |
| US6707078B1 | Dummy wordline for erase and bitline leakage | Physics | 24 | Expired |
| US6803275B1 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Electricity | 24 | Expired |
| US6969886B1 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Electricity | 18 | Expired |
| US7067377B1 | Recessed channel with separated ONO memory device | Electricity | 16 | Expired |
| US7009887B1 | Method of determining voltage compensation for flash memory devices | Physics | 16 | Expired |
| US6955965B1 | Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device | Electricity | 14 | Expired |
| US6944057B1 | Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference | Physics | 12 | Expired |
| US6803265B1 | Liner for semiconductor memories and manufacturing method therefor | Electricity | 11 | Expired |
| US6809033B1 | Innovative method of hard mask removal | Electricity | 8 | Expired |
| US6977195B1 | Test structure for characterizing junction leakage current | Electricity | 5 | Expired |
| US6813735B1 | I/O based column redundancy for virtual ground with 2-bit cell flash memory | Physics | 4 | Expired |
| US6730564B1 | Salicided gate for virtual ground arrays | Emerging Cross-Sectional Technologies | 2 | Expired |
| US7394125B1 | Recessed channel with separated ONO memory device | Electricity | 2 | Active |
| US7019366B1 | Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance | Electricity | 2 | Expired |
| US6936515B1 | Method for fabricating a memory device having reverse LDD | Electricity | 2 | Expired |
| US6979577B2 | Method and apparatus for manufacturing semiconductor device | Physics | 1 | Expired |
| US7074677B1 | Memory with improved charge-trapping dielectric layer | Emerging Cross-Sectional Technologies | 1 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.