Creating shallow junction transistors
US6936518B2 · kind B2 · utility
4Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A polysilicon structure may be defined on a semiconductor substrate using plasma doping to dope the sidewalls and upper surface of the polysilicon material as well as the source drain extensions. Shortly after plasma doping, the structure may be encapsulated within a suitable capping layer to prevent the removal of the thin surface doped regions during subsequent semiconductor processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.