Method and apparatus for delaying interfering accesses from other threads during transactional program execution
US6938130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.