Logic circuit having a functionally redundant transistor network
US6938223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics and signal integrity. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.