Method of manufacturing electronic device
US6938238B2 · kind B2 · utility
4Cited by
2References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Nov 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of forming a circuit pattern including fine pattern features and fine space, a hard mask layer is patterned with a first pattern defined by eliminating the fine space for merging the pattern features. Thereafter the hard mask layer is shrank. Next, the hard mask layer is patterned with a second pattern that is defined on the basis of the fine space. Finally, the circuit pattern is formed in an underlying layer using the hard mask layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.