Chamber wafer detection
US6938505B2 · kind B2 · utility
14Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Jan 7, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for detecting in chamber wafer position and process status are disclosed. A chamber includes a processing pedestal and plurality of lift pins. Each lift pin has an associated load cell for measuring the load exerted by the wafer on the lift pins. Mispositioned wafers or broken wafers will result in load measurements outside of expected ranges. Position of the wafer may be determined from the load distribution sensed on the lift pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.