Integration method of a semiconductor device having a recessed gate electrode
US6939765B2 · kind B2 · utility
14Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2003 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Dec 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.