Method of etching a layer in a trench and method of fabricating a trench capacitor

US6939805B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jorn Lutzen · Dresden, DE
• Barbara Schmidt · Santa Rosa, US
• Stefan Rongen · Dresden, DE
• Martin Schrems · Langenbruck, DE
• Daniel Kohler · Obermoschel, DE

Key dates

• Filing date: Sep 24, 2002
• Grant date: Sep 6, 2005
• Expiry date: May 16, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0387
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.