Increasing carrier mobility in NFET and PFET transistors on a common wafer

US6939814B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Victor Chan · Guilderland, US
• Haining Yang · Wappingers Falls, US

Key dates

• Filing date: Oct 30, 2003
• Grant date: Sep 6, 2005
• Expiry date: Oct 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/8311

Abstract

Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.