Trench isolated cross-point memory array
US6940113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2004 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Oct 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrod…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.