Pin electronics interface circuit
US6940271B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Jul 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.